1. Field of the Invention
The present invention relates to a semiconductor memory device capable of realizing the high-speed transmission of predecoded address signals, and of reducing power consumption using only part of its large-capacity memory.
2. Description of the Prior Art
It is well known that a CMOS memory has a construction shown in FIG. 1, wherein address signals A.sub.1 to An are supplied through address buffers 1a to 1n to a predecoder 2 and are predecoded.
The predecoded signals are then transmitted through predecoded signal lines 3a to 3n to a main decoder 4.
As shown in FIG. 1, the predecoded signal lines 3a to 3n have parasitic wire capacities C. The capacities C become larger with the increased length of the predecoded signal lines 3a to 3n. As the chips become larger in size along with increase in the memory capacity, the capacities C become larger.
In transmitting signals through the predecoded signal lines 3a to 3n with the capacities C, the capacities C need to be charged and discharged. Accordingly, it takes a long time to discharge and discharge the increased wire capacities C. Therefore, with the longer predecoded signal lines 3a to 3n, a delay time due to the capacities C is not ineligible, thus preventing address signals from being transmitted in high-speed.
Along with increase in the memory capacity, memory areas in the chip tend to be partly but not fully utilized.
However, in using only part of memory areas, all of its memory areas have been activated. Therefore, a stand-by current consumed by a semiconductor memory device is constant irrespective of memory bits to be used. As a result, even when only a limited number of bits are used, a large amount of stand-by current have been used in the same manner as in using all its memory areas.
Thus, in the case that a large-capacity memory device is contained in a system using large memory areas in the future but only part of its memory areas in the beginning, there causes such inconvenience that a large stand-by current is consumed even when the use of its memory areas is limited. Particularly, in a battery-operation system, the continuous operative time is shortened with the large current consumption, and consequently it is desired to reduce the current consumption. Therefore, in the case that a large-capacity semiconductor memory devices are contained in the system requiring only part of memory areas, it becomes advantageous that a large stand-by current is consumed.